ALLEGRO-DVT

Allegro DVT , the leading provider of video processing silicon IPs, today announced the immediate availability of its AL-D320 video decoder semiconductor IP core supporting the latest Versatile Video Coding (VVC/H.266) format. The AL-D320 core is the world’s first hardware IP to support the new VVC format with 8, 10 and 12-bit samples, chroma sampling of 4:2:0 and 4:2:2 and image resolutions and rates of up to 8K120. Added to this, the core continues to support H.264 and HEVC up to 12-bit and 4:4:4 chroma subsampling.

The Versatile Video Coding (VVC/H.266) format has been developed as the successor to the High Efficiency Video Coding (HEVC/H.265) format, with the aim of 30-50% better video compression for the same perceptual video quality. VVC supports resolutions up to 16K as well as 360° videos.

Nouar Hamze, CEO of Allegro DVT commented “The increased complexity of VVC requires HW based implementations for the decoding function to achieve the best trade-off between power consumption, performance and total cost of the solution.”

He added “The increase in complexity of leading-edge video codecs has lengthened development time. We have developed and released our VVC decoder IP early on to accelerate market adoption. Our release pre-empts the demand in a way that we believe will enable OEMs and semiconductor vendors to confidently move forward with the introduction of solutions with VVC decoding capability and therefore speed up the adoption of this new codec to unlock new use cases such as 8K broadcast worldwide.”

The AL-D320 employs a unique multi-format and multi-core architecture which allows scalability to seamlessly support additional video codecs such as AV1/VP9/HEVC/H.264 and higher decoding throughputs up to 8K60 and 8K120.
The release of this range of VVC decoder IP cores shows a continuation in Allegro DVT’s ability to consistently innovate and deliver at the highest level in the market. Building on existing production-proven video decoder semiconductor IP cores, the AL-D320 range of decoders provides end customers both early access to the latest technology while at the same time minimizing adoption risk.

AL-D320 decoder IP is immediately available for integration by SoC vendors in various technology nodes ranging from 28nm down to 5nm and below through a seamless and proven HW and SW integration kit.

About Allegro DVT

For more information: https://www.allegrodvt.com/

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